View LTC1289CCSWTRPBF_4251370.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 ltc1289 1289fb 3 volt single chip 12-bit data acquisition system single supply 3.3v or 3.3v operation software programmable features unipolar/bipolar conversions 4 differential/8 single-ended inputs variable data word length power shutdown built-in sample-and-hold direct 4-wire interface to most mpu serial ports and all mpu parallel ports 25khz maximum throughput rate available in 20-lead pdip and 20-lead sw packages single cell 3v 12-bit data acquisition system minimum guaranteed supply voltage: 2.7v resolution: 12 bits fast conversion time: 26 s max over temp low supply currents: 1.0ma the ltc 1289 is a 3v data acquisition component which contains a serial i/o successive approximation a/d con- verter. the device specifications are guaranteed at a supply voltage of 2.7v. it uses ltcmos tm switched ca- pacitor technology to perform a 12-bit unipolar, or 11-bit plus sign bipolar a/d conversion. the 8 channel input multiplexer can be configured for either single-ended or differential inputs (or combinations thereof). an on-chip sample and hold is included for all single-ended input channels. when the ltc1289 is idle it can be powered down in applications where low power consumption is desired. the serial i/o is designed to be compatible with industry standard full duplex serial interfaces. it allows either msb- or lsb- first data and automatically provides 2? comple- ment output coding in the bipolar mode. the output data word can be programmed for a length of 8, 12 or 16 bits. this allows easy interface to shift registers and a variety of processors. ltc1289 ta01 ltc1289 1n4148 10 f + 10 ? 1/4 ltc1079 +3v ?v to and from mpu + 22 f tantalum 1n4148 10k + lt1004-1.2 0.1 f 22 f 1n5817 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com dgnd v cc aclk sclk d in d out cs ref + ref v agnd boost cap + gnd cap v + osc lv v out ltc1044 10 f + + 22 f ?v 3v lithium for overvoltage protection on only one channel limit the input current to 15ma. for more than one channel limit the input current to 7ma per channel and 28ma for all channels. conversion results are not valid when the selected or any other channel is overvoltaged (v in < v or v in > v cc ). descriptio u features typical applicatio u , lt, ltc and ltm are registered trademarks of linear technology corporation. ltcmos is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. applicatio s u
2 ltc1289 1289fb the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) ltc1289b ltc1289c parameter conditions min typ max min typ max units offset error v cc = 2.7v 1.5 1.5 lsb (note 4) linearity error (inl) v cc = 2.7v 0.5 0.5 lsb (notes 4 and 5) gain error v cc = 2.7v 0.5 1.0 lsb (note 4) a u g w a w u w a r b s o lu t exi t i s (notes 1 and 2) co verter a d ultiplexer characteristics uu w supply voltage v cc to gnd or v ........................... 12v negative supply voltage (v ) .................... 6v to gnd voltage analog and reference inputs ... (v ) 0.3v to v cc + 0.3v digital inputs ........................................ 0.3v to 12v digital outputs ........................... 0.3v to v cc + 0.3v power dissipation ............................................. 500mw operating temperature range ltc1289bc, ltc1289cc ......................... 0 c to 70 c storage temperature range ................ 65 c to 150 c lead temperature (soldering, 10 sec.)................ 300 c wu u package / o rder i for atio consult ltc marketing for parts specified with wider operating temperature ranges. ltc1289bcn ltc1289ccn order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/ order part number ltc1289bcsw ltc1289ccsw order part number 1 2 3 4 5 6 7 8 9 10 top view j package, 20-lead ceramic dip n package, 20-lead plastic dip 20 19 18 17 16 15 14 13 12 11 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com dgnd v cc aclk sclk d in d out cs ref + ref v agnd t jmax = 110 c, ja = 100 c/w (n) t jmax = 110 c, ja = 150 c/w (sw) 1 2 3 4 5 6 7 8 9 10 top view sw package 20-lead plastic so wide 20 19 18 17 16 15 14 13 12 11 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com dgnd v cc aclk sclk din d out cs ref + ref v agnd obsolete package consider the n package for alternate source t jmax = 150 c, ja = 80 c/w (j) ltc1289bij ltc1289cij ltc1289bcj ltc1289ccj
3 ltc1289 1289fb ltc1289b ltc1289c symbol parameter conditions min typ max units f sclk shift clock frequency (note 6) 0 1.0 mhz f aclk a/d clock frequency (note 6) (note 10) 2.0 mhz t acc delay time from cs to d out data valid (note 9) 2 aclk cycles t smpl analog input sample time see operating sequence 7 sclk cycles t conv conversion time see operating sequence 52 aclk cycles t cyc total cycle time see operating sequence (note 6) 12 sclk + cycles 56 aclk t ddo delay time, sclk to d out data valid see test circuits 200 350 ns t dis delay time, cs to d out hi-z see test circuits 70 150 ns t en delay time, 2nd aclk to d out enabled see test circuits 130 250 ns t hcs hold time, cs after last sclk (note 6) 0 ns t hdi hold time, d in after sclk (note 6) 50 ns t hdo time output data remains valid after sclk 50 ns t f d out fall time see test circuits 40 100 ns t r d out rise time see test circuits 40 100 ns t sudi setup time, d in stable before sclk (note 6 and 9) 50 ns t sucs setup time, cs before clocking in (note 6 and 9) 2 aclk cycles first address bit + 180ns t whcs cs high time during conversion (note 6) 52 aclk cycles c in input capacitance analog inputs on channel 100 pf analog inputs off channel 5 pf digital inputs 5 pf the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) co verter a d ultiplexer characteristics uu w ltc1289b ltc1289c parameter conditions min typ max min typ max units minimum resolution for 12 12 bits which no missing codes are guaranteed analog and ref input range (note 7) (v ) 0.05v to v cc + 0.05v (v ) 0.05v to v cc + 0.05v v on channel leakage current on channel = 3v 1 1 a (note 8) off channel = 0v on channel = 0v 1 1 a off channel = 3v off channel leakage current on channel = 3v 1 1 a (note 8) off channel = 0v on channel = 0v 1 1 a off channel = 3v ac characteristics the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3)
4 ltc1289 1289fb ltc1289b ltc1289c symbol parameter conditions min typ max units v ih high level input voltage v cc = 3.6v 2.1 v v il low level input voltage v cc = 3.0v 0.45 v i ih high level input current v in = v cc 2.5 a i il low level input current v in = 0v 2.5 a v oh high level output voltage v cc = 3.0v v i o = 20 a 2.90 i o = 400 a 2.7 2.85 v ol low level output voltage v cc = 3.0v v i o = 20 a 0.05 i o = 400 a 0.10 0.3 i oz high z output leakage v out = v cc , cs high 3 a v out = 0v, cs high ? a i source output source current v out = 0v 10 ma i sink output sink current v out = v cc 9ma i cc positive supply current cs high 1.5 5 ma cs high, power shutdown, aclk off 1.0 10 a i ref reference current v ref = 2.5v 10 50 a i negative supply current cs high 150 a e lectr ic al c c hara ter st ics digital a d u i dc note 7: two on-chip diodes are tied to each analog input which will conduct for analog voltages one diode drop below gnd or one diode drop above v cc . be careful during testing at low v cc levels, as high level analog inputs can cause this input diode to conduct, especially at elevated temperature, and cause errors for inputs near full scale. this spec allows 50mv forward bias of either diode. this means that as long as the analog input does not exceed the supply voltage by more than 50mv, the output code will be correct. note 8: channel leakage current is measured after the channel selection. note 9: to minimize errors caused by noise at the chip select input, the internal circuitry waits for two aclk falling edges after a chip select falling edge is detected before responding to control input signals. therefore, no attempt should be made to clock an address in or data out until the minimum chip select set-up time has elasped. see typical peformance characteristics curves for additional information (t sucs vs v cc ). note 10: increased leakage currents at elevated temperatures cause the s/h to droop, therefore it's recommended that f aclk 125khz at 85 c and f aclk 15khz at 25 c. note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to ground with dgnd, agnd and ref wired together (unless otherwise noted). note 3: v cc = 3v, v ref + = 2.5v, v ref ?= 0v, v = 0v for unipolar mode and 3v for bipolar mode, aclk = 2.0mhz unless otherwise specified. note 4: these specs apply for both unipolar and bipolar modes. in bipolar mode, one lsb is equal to the bipolar input span (2v ref ) divided by 4096. for example, when v ref = 2.5v, 1lsb(bipolar) = 2(2.5)/4096 = 1.22mv. v = 2.7v for bipolar mode. note 5: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 6: recommended operating conditions. the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3)
5 ltc1289 1289fb cc hara terist ics uw a t y p i ca lper f o r c e supply current vs temperature change in linearity vs reference voltage change in gain vs reference voltage supply current vs supply voltage temperature ( c) ?0 1.3 supply current (ma) 1.4 1.5 1.6 1.7 ?5 ?0 50 ltc 1289 tpc02 1.8 1.9 52035 65 95 80 aclk = 2mhz v cc = 3v unadjusted offset voltage vs reference voltage change in offset vs temperature maximum aclk frequency vs source resistance * maximum aclk frequency represents the aclk frequency at which a 0.1lsb shift in the error at any code transition from its 2mhz value is first detected. supply voltage (v) 2.7 0.8 supply current (ma) 1.0 1.4 1.6 1.8 2.8 2.2 2.9 3.1 3.2 3.6 ltc1289 tpc01 1.2 2.4 2.6 2.0 2.8 3.0 3.3 3.4 3.5 aclk = 2mhz t a = 25 c reference voltage (v) 0 0 offset (lsb = 1/4096 v ref ) 0.1 0.3 0.4 0.5 1.0 2.0 3.0 0.9 ltc1289 tpc03 0.2 0.5 1.5 0.6 0.7 0.8 2.5 v cc = 3v v os = 0.250mv v os = 0.125mv change in linearity vs temperature ambient temperature ( c) ?0 magnitude of linearity change (lsb) 0.3 0.4 0.5 0 40 100 ltc1289 tpc07 0.2 0.1 0 ?0 ?0 20 60 80 v cc = 3v v ref = 2.5v aclk = 2mhz ambient temperature ( c) ?0 magnitude of gain change (lsb) 0.3 0.4 0.5 0 40 100 ltc1289 tpc08 0.2 0.1 0 ?0 ?0 20 60 80 v cc = 3v v ref = 2.5v aclk = 2mhz change in gain vs temperature r source ( ? ) 100 0 maximum aclk frequency* (mhz) 2 3 1k 10 k 100k ltc1289 tpc09 1 v cc = 3v v ref = 2.5v t a = 25 c + input input v in r source ambient temperature ( c) ?0 magnitude of offset change (lsb) 0.3 0.4 0.5 0 40 100 ltc1289 tpc06 0.2 0.1 0 ?0 ?0 20 60 80 v cc = 3v v ref = 2.5v aclk = 2mhz reference voltage (v) 0 change in gain (lsb = 1/4096 v ref ) 0.15 0.20 0.25 2.0 ltc1289 tpc05 0.05 0.15 0.25 0.5 1.0 1.5 2.5 3.0 0.10 0.05 0 0.10 0.20 v cc = 3v reference voltage (v) 0 0 change in linearity (lsb = 1/4096 v ref ) 0.1 0.2 0.3 0.4 0.5 0.5 1.0 1.5 2.0 ltc1289 tpc04 2.5 3.0 v cc = 3v
6 ltc1289 1289fb cc hara terist ics uw a t y p i ca lper f o r c e supply current (power shutdown) vs temperature maximum filter resistor vs cycle time sample and hold acquisition time vs source resistance supply current (power shutdown) vs aclk input channel leakage current vs temperature noise error vs reference voltage ambient temperature ( c) ?0 0 input channel leakage current (na) 100 300 400 500 1000 700 ?0 30 50 130 ltc1289 tpc14 200 800 900 600 ?0 10 70 90 110 on channel off channel guaranteed reference voltage (v) 0 peak-to-peak noise error (lsb) 0.6 0.8 1.0 2.0 0.4 0.2 0 0.5 1.0 1.5 2.5 3.0 ltc1289 tpc15 ltc1289 noise = 200 v p-p cycle time ( s) maximum r filter ** ( ? ) 10 100 1k 10k 10 1000 10000 ltc1289 tpc10 1 100 + v in c filter 1 f r filter r source + ( ? ) 100 1 s & h aquisition time to 0.02% ( s) 10 100 1k 10k ltc1289 tpc11 + v in r source + v ref = 2.5v v cc = 3v t a = 25 c 0v to 2.5v input step ambient temperature ( c) ?0 0 supply current ( a) 0.2 0.6 0.8 1.0 2.0 1.4 ?0 20 40 ltc1289 tpc12 0.4 1.6 1.8 1.2 ?0 0 60 80 100 aclk off during power shutdown aclk frequency (khz) 200 supply current ( a) 12 14 16 800 10 8 400 600 1000 6 4 18 ltc1298 tpc13 v cc = 3v cmos logic swings t sucs vs supply voltage power consumption with power shutdown vs f sample supply voltage (v) 2.7 0 2aclk + ns 50 100 150 200 250 300 2.8 2.9 3.3 3.4 ltc1289 tpc16 3.6 3.0 3.1 3.2 3.5 t a = 25 c ** maximum r filter represents the filter resistor value at which a 0.1lsb change in full scale error from its value at r filter = 0 is first detected. f sample (hz) 10 icc ( a) 100 1000 10000 1 100 1000 10000 ltc1289 tpc17 1 10 v cc = 3v v ref = 2.5v aclk = 2mhz cmos logic swings three conversions/cycle
7 ltc1289 1289fb pi fu ctio s u uu block diagram input shift register sample and hold 12-bit capacitive dac v cc 20 analog input mux 1 2 3 4 5 6 7 8 9 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com d out 16 sclk 18 control and timing 15 cs ltc1289 bd 17 ref + 14 dgnd 10 agnd 11 v 12 ref 13 comp output shift register d in 19 aclk 12-bit sar ch0 ?ch7 (pins 1 ?8): analog inputs. the analog in- puts must be free of noise with respect to agnd. com (pin 9): common. the common pin defines the zero reference point for all single-ended inputs. it must be free of noise and is usually tied to the analog ground plane. dgnd (pin 10): digital ground. this is the ground for the internal logic. tie to the ground plane. agnd (pin 11): analog ground. agnd should be tied di- rectly to the analog ground plane. v ? (pin 12): negative supply. tie v to the most negative potential in the circuit. (ground in single supply applica- tions.) ref , ref + (pins 13,14) reference inputs. the reference inputs must be kept free of noise with respect to agnd. cs (pin 15): chip select input. a logic low on this input enables data transfer. d out (pin 16): digital data output. the a/d conversion result is shifted out of this output. d in (pin 17): digital input. the a/d configuration word is shifted into this input. sclk (pin 18): shift clock. this clock synchronizes the serial data transfer. aclk (pin 19): a/d conversion clock. this clock con- trols the a/d conversion process. v cc (pin 20): positive supply. this supply must be kept free of noise and ripple by bypassing directly to the analog ground plane.
8 ltc1289 1289fb test circuits 3v a a i off i on polarity off channels on channel ltc1283 tc01 on and off channel leakage current voltage waveforms for t en and t dis voltage waveforms for d out rise and fall times, t r ,t f d out 0.6v 2.1v t r t f ltc1289 tc04 load circuit for t dis and t en load circuit for t ddo , t r and t f voltage waveforms for d out delay time, t ddo sclk d out 0.45v t ddo 0.6v 2.1v ltc1289 tc03 d out 1.5v 3k 100pf test point ltc1289 tc02 d out 3k 100pf test point 3v t dis waveform 2, t en t dis waveform 1 ltc1289 tc05 d out waveform 1 (see note 1) t dis 90% 10% d out waveform 2 (see note 2) cs note 1: waveform 1 is for an output with conditions such that the output is high unless disabled by the output control. note 2: waveform 2 is for an output with internal conditions such that the output is low unless disabled by the output control. ltc1289 tc06 t en 2.1v 0.6v aclk 12 2.1v
9 ltc1289 1289fb u s a o pp l ic at i wu u i for atio previous conversion is output on the d out line. at the end of the data exchange the requested conversion begins and cs should be brought high. after t conv , the conversion is complete and the results will be available on the next data transfer cycle. as shown below, the result of a conversion is delayed by one cs cycle from the input word requesting it. operating sequence (example: differential inputs (ch3-ch2), bipolar, msb-first and 12-bit word length) input data word the ltc1289 8-bit data word is clocked into the d in input on the first eight rising sclk edges after chip select is recognized. further inputs on the d in pin are then ignored until the next cs cycle. the eight bits of the input word are defined as follows: d in d out d out word 0 d in word 1 data transfer d out word 2 d in word 3 d out word 1 d in word 2 data transfer t conv a/d conversion t conv a/d conversion ltc1289 ai01 sgl/ diff select 1 select 0 uni msbf wl1 mux address msb-first/ lsb-first unipolar/ bipolar word length ltc1289 ai02 odd/ sign wl0 123456789101112 t conv don't care don't care t cyc shift configuration word in t smpl shift a/d result out and new configuration word in b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 (sb) ltc1289 ai03 sclk d in d out cs the ltc1289 is a data acquisition component which contains the following functional blocks: 1. 12-bit successive approximation capacitive a/d converter 2. analog multiplexer (mux) 3. sample-and-hold (s/h) 4. synchronous, full duplex serial interface 5. control and timing logic digital considerations serial interface the ltc1289 communicates with microprocessors and other external circuitry via a synchronous, full duplex, four wire serial interface (see operating sequence). the shift clock (sclk) synchronizes the data transfer with each bit being transmitted on the falling sclk edge and captured on the rising sclk edge in both transmitting and receiving systems. the data is transmitted and received simulta- neously (full duplex). data transfer is initiated by a falling chip select (cs) signal. after the falling cs is recognized, an 8-bit input word is shifted into the d in input which configures the ltc1289 for the next conversion. simultaneously, the result of the
10 ltc1289 1289fb u s a o pp l ic at i wu u i for atio mux address the first four bits of the input word assign the mux configuration for the requested conversion. for a given channel selection, the converter will measure the voltage between the two channels indicated by the + and ?signs in the selected row of table 1. note that in differential mux address differential channel selection table 1. multiplexer channel selection mux address sgl/ diff select 1 0 odd sign 10 00 + 10 01 + 10 10 + 10 11 + 11 00 + 11 01 + 11 10 + 11 11 + sgl/ diff odd sign select 1 0 00 00+ 00 01 + 00 10 + 00 11 + 01 00+ 01 01 + 01 10 + 01 11 + 0 1 23 4 56 7 0 1 2 3 4 5 6 7 com single-ended channel selection mode (sgl/diff = 0) measurements are limited to four adjacent input pairs with either polarity. in single-ended mode, all input channels are measured with respect to com. figure 1. examples of multiplexer options on the ltc1289 0 1 2 3 4 5 6 7 channel com ( ) 8 single-ended + + + + + + + 0,1 channel 4 differential 2,3 4,5 6,7 + ( ) + + ( ) + ( ) + ( ) ( + ) ( + ) ( + ) ( + ) 4 5 6 7 channel com ( ) combinations of differential and single-ended + + + + + + 0,1 2,3 com (unused) changing the mux assignment ?n the fly com ( ) 4,5 6,7 5,4 1st conversion 2nd conversion + + + + + 7 6 { { { { { { { { { { ltc1289 aif01
11 ltc1289 1289fb u s a o pp l ic at i wu u i for atio unipolar/bipolar (uni) the fifth input bit (uni) determines whether the conver- sion will be unipolar or bipolar. when uni is a logical one, a unipolar conversion will be performed on the selected unipolar transfer curve (uni = 1) input voltage. when uni is a logical zero, a bipolar conver- sion will result. the input span and code assignment for each conversion type are shown in the figures below. unipolar output code (uni = 1) bipolar transfer curve (uni = 0) bipolar output code (uni = 0) output code 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 input voltage v ref ?1lsb v ref ?2lsb 1lsb 0v i nput voltage (v ref = 2.5v) 2.4994v 2.4988v 0.0006v 0v ltc1289 ai04a 0v 1lsb v ref ?2lsb v ref ?1lsb v ref v in 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 ltc1289 ai04b 1lsb v ref ?2lsb v ref ?1lsb v ref v in 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 ?lsb ?lsb ? ref ? ref + 1lsb ltc1289 ai05b output code 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 input voltage ?lsb ?lsb ?v ref ) + 1lsb ?(v ref ) input voltage (v ref = 2.5v) 0.0012v 0.0024v 2.4988v 2.5000v output code 0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 input voltage v ref ?1lsb v ref ?2lsb 1lsb 0v input voltage (v ref = 2.5v) 2.4988v 2.4976v 0.0012v 0v ltc1289 ai05a
12 ltc1289 1289fb u s a o pp l ic at i wu u i for atio the following discussion will demonstrate how the two reference pins are to be used in conjunction with the analog input multiplexer. in unipolar mode the input span of the a/d is set by the difference in voltage on the ref + pin and the ref pin. in the bipolar mode the input span is twice the difference in voltage on the ref + pin and the ref pin. in the unipolar mode the lower value of the input span is set by the voltage on the com pin for single-ended inputs and by the voltage on the minus input pin for differential inputs. for the bipolar mode of operation the voltage on the com pin or the minus input pin sets the center of the input span. the upper and lower value of the input span can now be summarized in the following table: example 2 (diff.): in in + in + 2v example 3 (diff.): in ?2v in + in + 2v. msb-first/lsb-first format (msbf) the output data of the ltc1289 is programmed for msb- first or lsb-first sequence using the msbf bit. for msb- first output data, the input word clocked to the ltc1289 should always contain a logical one in the sixth bit location (msbf bit). likewise for lsb-first output data the input word clocked to the ltc1289 should always contain a zero in the msbf bit location. the msbf bit affects only the order of the output data word. the order of the input word is unaffected by this bit. the reference voltages ref + and ref can fall between v cc and v , but the difference (ref + ?ref ) must be less than or equal to v cc . the input voltages must be less than or equal to v cc and greater than or equal to v . the following examples are for a single-ended input con- figuration. example 1: let v cc = 3.3v, v = 0v, ref + = 3v, ref = 1v and com = 0v. unipolar mode of operation. the resulting input span is 0v in + 2v. example 2: the same conditions as example 1 except com = 1v. the resulting input span is 1v in + 3v. note if in + 3v the resulting d out word is all 1?. if in + 1v then the resulting d out word is all 0?. example 3: let v cc = 3.3v, v = 3.3v, ref + = 3v, ref = 1v and com = 1v. bipolar mode of operation. the resulting input span is 1v in+ 3v. for differential input configurations with the same condi- tions as in the above three examples the resulting input spans are as follows: example 1 (diff.): in in + in + 2v word length (wl1, wl0) and power shutdown the last two bits of the input word (wl1 and wl0) program the output data word length and the power shutdown feature of the ltc1289. word lengths of 8, 12 or 16 bits can be selected according to the following table. the wl1 and wl0 bits in a given d in word control the length of the present, not the next, d out word. wl1 and wl0 are never ?on? cares?and must be set for the correct d out word length even when a ?ummy?d in word is sent. on any transfer cycle, the word length should be made equal to the number of sclk cycles sent by the mpu. power down will occur when wl1 = 0 and wl0 = 1 is selected. the previous result will be clocked out as a 10 bit word so a ?ummy?onversion is required before powering down the ltc1289. conversions are resumed once cs goes low or an sclk is applied, if cs is already low. input configuration unipolar mode bipolar mode single-ended lower value com ?ref + ?ref ) + com upper value (ref + ?ref ) + com (ref + ?ref ) + com differential lower value in ?ref + ?ref ) + in upper value (ref + ?ref ) + in (ref + ?ref ) + in msbf 0 1 output format lsb-first msb-first ltc1289 ai06 wl1 0 0 1 1 output word length 8 bits power shutdown 12 bits 16 bits ltc1289 ai07 wl0 0 1 0 1
13 ltc1289 1289fb u s a o pp l ic at i wu u i for atio figure 2. data output (d out ) timing with different word lengths t smpl b11 1 t conv b10 b9 b8 b7 b4 (sb) 8-bit word length sclk cs d out lsb-first t smpl b11 1 t conv (sb) 12-bit word length sclk cs d out lsb-first 10 12 d out msb-first d out msb-first (sb) t smpl 1 t conv 16-bit word length 12 16 fill zeros * ** * in unipolar mode, these bits are filled with zeros. in bipolar mode, the sign bit is extended into these locations. ltc1289 aif02 b6 b5 b0 b1 b2 b3 b4 b7 b5 b6 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 sclk cs d out lsb-first d out msb-first b11 (sb) (sb) b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 the last four bits are truncated
14 ltc1289 1289fb u s a o pp l ic at i wu u i for atio deglitcher a deglitching circuit has been added to the chip select input of the ltc1289 to minimize the effects of errors caused by noise on that input. this circuit ignores changes in state on the cs input that are shorter in duration than one aclk cycle. after a change of state on the cs input, the ltc1289 waits for two falling edge of the aclk before recognizing a valid chip select. one indication of cs recognition is the d out line becoming active (leaving the hi-z state). note that the deglitching applies to both the rising and falling cs edges. cs low during conversion in the normal mode of operation, cs is brought high during the conversion time. the serial port ignores any sclk activity while cs is high. the ltc1289 will also operate with cs low during the conversion. in this mode, sclk must remain low during the conversion as shown in the following figure. after the conversion is complete, the d out line will become active with the first output bit. then the data transfer can begin as normal. figure 4. cs low during conversion figure 3. cs high during conversion low cs recognized internally high cs recognized internally cs aclk d out hi-z valid output ltc1289 ai08 cs aclk d out hi-z valid output ltc1289 ai08a don't care b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 shift result out and new address in sclk cs d out d in t smpl sample analog input shift mux address in ltc1289 aif03 48 to 52 aclk cyc don't care b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b11b10b9b8b7b6b5b4b3b2b1b0 shift result out and new address in sclk cs d out d in t smpl sample analog input shift mux address in ltc1289 aif04 48 to 52 aclk cyc sclk must remain low
15 ltc1289 1289fb u s a o pp l ic at i wu u i for atio logic levels the logic level standards for this supply range have not been well defined. what standards that do exist are not universally accepted. the trip point on the logic inputs of the ltc1289 is 0.28 v cc . this makes the logic inputs compatible with hc type logic levels and processors that are specified at 3.3v. the output d out is also compatible with the above standards. the following summarizes such levels. the ltc1289 can be driven with 5v logic even when v cc is at 3.3v. this is due to a unique input protection device that is found on the ltc1289. microprocessor interfaces the ltc1289 can interface directly (without external hard- ware) to most popular microprocessor (mpu) synchro- nous serial formats. if an mpu without a serial interface is used, then four of the mpu? parallel port lines can be programmed to form the serial link to the ltc1289. many of the popular mpu's can operate with 3v supplies. for example the mc68hc11 is an mpu with a serial format (spi). likewise parallel mpu? that have the 8051 type architecture are also capable of operating at this voltage range. the code for these processors remains the same and can be found in the ltc1290 datasheet or application notes an36a and an36b. sharing the serial interface the ltc1289 can share 3-wire serial interface with other peripheral components or other ltc1289s (see figure 5). in this case, the cs signals decide which ltc1289 is being addressed by the mpu. analog considerations 1. grounding the ltc1289 should be used with an analog ground plane and single point grounding techniques. pin 11 (agnd) should be tied directly to this ground plane. pin 10 (dgnd) can also be tied directly to this ground plane because minimal digital noise is generated within the chip itself. pin 20 (v cc ) should be bypassed to the ground plane with a 22 f tantalum with leads as short as possible. pin 12 (v ) should be bypassed with a 0.1 f ceramic disk. for single supply applications, v ? can be tied to the ground plane. it is also recommended that pin 13 (ref ) and pin 9 (com) be tied directly to the ground plane. all analog inputs should be referenced directly to the single point ground. digital inputs and outputs should be shielded from and/or routed away from the reference and analog circuitry. figure 5. several ltc1289s sharing one 3-wire serial interface v oh (no load) v cc - 0.1v v ol (no load) 0.1v v oh 0.9 v cc v ol 0.1 v cc v ih 0.7 v cc v il 0.2 v cc 8 channels 8 channels 8 channels 3 3 3 3 3-wire serial interface to other peripherals or ltc1289s 2 10 output port serial data mpu ltc1289 aif05 ltc1289 cs ltc1289 cs ltc1289 cs
16 ltc1289 1289fb u s a o pp l ic at i wu u i for atio figure 6 shows an example of an ideal ground plane design for a two-sided board. of course, this much ground plane will not always be possible, but users should strive to get as close to this ideal as possible. 2. bypassing for good performance, v cc must be free of noise and ripple. any changes in the v cc voltage with respect to analog ground during a conversion cycle can induce errors or noise in the output code. v cc noise and ripple can be kept below 0.5mv by bypassing the v cc pin directly to the analog ground plane with a 22 f tantalum capacitor and leads as short as possible. the lead from the device to the v cc supply should also be kept to a minimum and the v cc supply should have a low output impedance such as that obtained from a voltage regulator (e.g., lt1117). using a battery to power the ltc1289 will help reduce the amount of bypass capacitance required on the v cc pin. a battery placed close to the device will only require 10 f to adequately bypass the supply pin. figure 7 shows the effect of poor v cc bypassing. figure 8a shows the settling of a lt1117 low dropout regulator with a 22 f bypass capacitor. the noise and ripple is approximately 0.5mv. figure 8b shows the response of a lithium battery with a 10 f bypass capacitor. the noise and ripple is kept below 0.5mv. figure 7. poor v cc bypassing. noise and ripple can cause a/d errors. figure 8a. lt1117 regulator with 22 f bypassing on v cc horizontal: 20 s/div 5v/div cs 0.5mv/div v cc figure 8b. lithium battery with 10 f bypassing on v cc horizontal: 20 s/div figure 6. example ground plane for the ltc1289 v 22 f tantalum v cc ltc1289 aif06 0.1 f ceramic disk analog ground plane 0.1 f 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 0.5mv/div 5v/div cs v cc vertical: 0.5mv/div horizontal: 10 s/div
17 ltc1289 1289fb u s a o pp l ic at i wu u i for atio 3. analog inputs because of the capacitive redistribution a/d conversion techniques used, the analog inputs of the ltc1289 have capacitive switching input current spikes. these current spikes settle quickly and do not cause a problem. how- ever, if large source resistances are used or if slow settling op amps drive the inputs, care must be taken to insure that the transients caused by the current spikes settle com- pletely before the conversion begins. source resistance the analog inputs of the ltc1289 look like a 100pf capacitor (c in ) is series with a 1500 ? resistor (r on ) as shown in figure 9. this value for r on is for v cc = 2.7v. with larger supply voltages r on will be reduced. for example with v cc = 2.7v and v = 2.7v r on becomes 500 ? . c in gets switched between the selected ??and inputs once during each conversion cycle. large external source resistors and capacitances will slow the settling of figure 10. ??and ?input settling windows the inputs. it is important that the overall rc time con- stants be short enough to allow the analog inputs to completely settle within the allotted time. ??input settling this input capacitor is switched onto the ??input during the sample phase (t smpl , see figure 10). the sample phase starts at the 4th sclk cycle and lasts until the falling edge of the last sclk (the 8th, 12th or 16th sclk cycle depending on the selected word length). the voltage on the ??input must settle completely within this sample time. minimizing r source + and c1 will improve the input settling time. if large ??input source resistance must be used, the sample time can be increased by using a slower sclk frequency or selecting a longer word length. with the minimum possible sample time of 4 s, r source + < 2k and c1 < 20pf will provide adequate settling . ?input settling at the end of the sample phase the input capacitor switches to the ?input and the conversion starts (see figure 10). during the conversion, the ??input voltage is effectively ?eld?by the sample and hold and will not affect the conversion result. however, it is critical that the ?input voltage be free of noise and settle completely during the first four aclk cycles of the conversion time. minimizing r source and c2 will improve settling time. if large input source resistance must be used, the time allowed for figure 9. analog input equivalent circuit sclk cs ??input aclk 1289 aif10 1234 ?? ?? ?? mux address shifted in t smpl last sclk (8th, 12th or 16th depending on work length) 1 234 1st bit test ?input must settle during this time sample hold ??input must settle during this time ?input ?? 4th sclk r on = 1.5k last sclk c in = 100pf ltc1289 ? input r source + v in + c1 input r source v in c2 ltc1289 aif09
18 ltc1289 1289fb u s a o pp l ic at i wu u i for atio settling can be extended by using a slower aclk fre- quency. at the maximum aclk rate of 2mhz, r source < 200 ? and c2 < 20pf will provide adequate settling. input op amps when driving the analog inputs with an op amp it is important that the op amp settle within the allowed time (see figure 10). again, the ??and ?input sampling times can be extended as described above to accommo- date slower op amps. for single supply low voltage applications the lt1006, lt1013 and lt1014 can be made to settle well even with the minimum settling win- dows of 4 s (??input) and 2 s (?input) which occur at the maximum clock rates (aclk = 2mhz and sclk = 1mhz). figures 11 and 12 show examples of adequate and poor op amp settling. the lt1077, lt1078 or lt1079 can be used here to reduce power consumption. placing an rc network at the output of the op amps will improve the settling response and also reduce the broadband noise. rc input filtering it is possible to filter the inputs with an rc network as shown in figure 13. for large values of c f (e.g., 1 f), the capacitive input switching currents are averaged into a net dc current. therefore, a filter should be chosen with a small resistor and large capacitor to prevent dc drops across the resistor. the magnitude of the dc current is approximately i dc = 100pf v in /t cyc and is roughly proportional to v in . when running at the minimum cycle time of 40 s, the input current equals 6.3 a at v in = 2.5v. in this case, a filter resistor of 10 ? will cause 0.1lsb of full-scale error. if a larger filter resistor must be used, errors can be eliminated by increasing the cycle time as shown in the typical curve of maximum filter resistor vs cycle time. input leakage current input leakage currents can also create errors if the source resistance gets too large. for instance, the maximum input leakage specification of 1 a (at 85 c) flowing through a source resistance of 1k ? will cause a voltage drop of 1mv or 1.6lsb with v ref = 2.5v. this error will be much reduced at lower temperatures because leakage drops rapidly (see typical curve of input channel leakage cur- rent vs temperature). noise coupling into inputs high source resistance input signals (>500 ? ) are more sensitive to coupling from external sources. it is prefer- able to use channels near the center of the package (i.e., ch2-ch7) for signals which have the highest output resistance because they are essentially shielded by the horizontal: 500ns/div figure 11. adequate settling of op amps driving analog input vertical: 5mv/div figure 13. rc input filtering r filter v in c filter ltc1289 aif13 ltc1289 ? i idc horizontal: 20 s/div figure 12. poor op amp settling can cause a/d errors vertical: 5mv/div
19 ltc1289 1289fb figure 14. reference input equivalent circuit r on 8pf ?40pf ltc1289 ref + r out v ref every 4 aclk cycles 14 13 ref ltc1289 aif14 pins on the package ends (dgnd and ch0). grounding any unused inputs (especially the end pin, ch0) will also reduce outside coupling into high source resistances. 4. sample and hold single-ended inputs the ltc1289 provides a built-in sample and hold (s&h) function for all signals acquired in the single-ended mode (com pin grounded). this sample and hold allows the ltc1289 to convert rapidly varying signals (see typical curve of s&h acquisition time vs source resistance). the input voltage is sampled during the t smpl time as shown in figure 10. the sampling interval begins after the fourth mux address bit is shifted in and continues during the remainder of the data transfer. on the falling edge of the final sclk, the s&h goes into hold mode and the conver- sion begins. the voltage will be held on either the 8th, 12th or 16th falling edge of the sclk depending on the word length selected. differential inputs with differential inputs or when the com pin is not tied to ground, the a/d no longer converts just a single voltage but rather the difference between two voltages. in these cases, the voltage on the selected ??input is still sampled and held and therefore may be rapidly time varing just as in single ended mode. however, the voltage on the se- lected ?input must remain constant and be free of noise and ripple throughout the conversion time. otherwise, the differencing operation may not be performed accurately. the conversion time is 52 aclk cycles. therefore, a change in the ?input voltage during this interval can cause conversion errors. for a sinusoidal voltage on the ?input this error would be: v error (max) = v peak 2 f(? where f(? is the frequency of the ?input voltage, v peak is its peak amplitude and f aclk is the frequency of the aclk. in most cases v error will not be significant. for u s a o pp l ic at i wu u i for atio a 60hz signal on the ?input to generate a 1/4lsb error (150 v) with the converter running at aclk = 2mhz, its peak value would have to be 15mv. 5. reference inputs the voltage between the reference inputs of the ltc1289 defines the voltage span of the a/d converter. the refer- ence inputs will have transient capacitive switching cur- rents due to the switched capacitor conversion technique (see figure 14). during each bit test of the conversion (every 4 aclk cycles), a capacitive current spike will be generated on the reference pins by the a/d. these current spikes settle quickly and do not cause a problem. how- ever, if slow settling circuitry is used to drive the reference inputs, care must be taken to insure that transients caused by these current spikes settle completely during each bit test of the conversion. when driving the reference inputs, two things should be kept in mind: 1. transients on the reference inputs caused by the capacitive switching currents must settle completely during each bit test (each 4 aclk cycles). figures 15 and 16 show examples of both adequate and poor settling. using a slower aclk will allow more time for the reference to settle. however, even at the maximum aclk rate of 2mhz most references and op amps can be made to settle within the 2 s bit time. for example an lt1019 used in the shunt mode with a 10 f bypass capacitor will settle adequately. to minimize power an lt1004-2.5 can be used with a 10 f bypass capacitor. for lower value references the lt1004-1.2 with a 1 f bypass capacitor can be used. 52 f aclk
20 ltc1289 1289fb u s a o pp l ic at i wu u i for atio figure 15. adequate reference settling horizontal: 1 s/div vertical: 0.5mv/div 2. it is recommended that ref input be tied directly to the analog ground plane. if ref is biased at a voltage other than ground, the voltage must not change during a conversion cycle. this voltage must also be free of noise and ripple with respect to analog ground. 6. reduced reference operation the effective resolution of the ltc1289 can be increased by reducing the input span of the converter. the ltc1289 exhibits good linearity and gain over a wide range of reference voltages (see typical curves of linearity and gain error vs reference voltage). however, care must be taken when operating at low values of v ref because of the reduced lsb step size and the resulting higher accuracy requirement placed on the converter. the following factors must be considered when operating at low v ref values: 1. offset 2. noise offset with reduced v ref the offset of the ltc1289 has a larger effect on the output code when the a/d is operated with reduced reference voltage. the offset (which is typically a fixed voltage) becomes a larger fraction of an lsb as the size of the lsb is reduced. the typical curve of unadjusted offset error vs reference voltage shows how offset in lsbs is related to reference voltage for a typical value of v os . for example, a v os of 0.1mv which is 0.2lsb with a 2.5v reference becomes 0.4lsb with a 1.25v reference. if this offset is unacceptable, it can be corrected digitally by the receiving system or by offsetting the ?input to the ltc1289. noise with reduced v ref the total input referred noise of the ltc1289 can be reduced to approximately 200 v peak-to-peak using a ground plane, good bypassing, good layout techniques and minimizing noise on the reference inputs. this noise is insignificant with a 2.5v reference but will become a larger fraction of an lsb as the size of the lsb is reduced. the typical curve of noise error vs reference voltage shows the lsb contribution of this 200 v of noise. for operation with a 2.5 reference, the 200 v noise is only 0.32lsb peak-to-peak. in this case, the ltc1289 noise will contribute virtually no uncertainty to the output code. however, for reduced references, the noise may become a significant fraction of an lsb and cause undesirable jitter in the output code. for example, with a 1.25v reference, this same 200 v noise is 0.64lsb peak-to-peak. this will reduce the range of input voltages over which a stable output code can be achieved by 0.64lsb. in this case averaging readings may be necessary. this noise data was taken in a very clean setup. any setup induced noise (noise or ripple on v cc , v ref , v in or v ) will add to the internal noise. the lower the reference voltage to be used, the more critical it becomes to have a clean, noise-free setup. figure 16. poor reference settling can cause a/d errors horizontal: 1 s/div vertical: 0.5mv/div
21 ltc1289 1289fb output spectrum of the ltc1289 is shown in figures 17a and 17b. the input (f in ) frequencies are 1khz and 12khz with the sampling frequency (f s ) at 25khz. the snr obtained from the plot are 72.92db and 72.23db. rewriting the snr expression it is possible to obtain the equivalent resolution based on the snr measurement. this is the so-called effective number of bits (enob). for the example shown in figures 17a and 17b, n = 11.8 bits and 11.7 bits, respectively. figure 18 shows a plot of enob as a function of input frequency. the curve shows the a/d? enob remain in the range of 11.8 to 11.7 for input frequencies up to f s /2 u s a o pp l ic at i wu u i for atio 7. ltc1289 ac characteristics two commonly used figures of merit for specifying the dynamic performance of the a/d? in digital signal pro- cessing applications are the signal-to-noise ratio (snr) and the ?ffective number of bits (enob).?snr is defined as the ratio of the rms magnitude of the fundamental to the rms magnitude of all the nonfundamental signals up to the nyquist frequency (half the sampling frequency). the theoretical maximum snr for a sine wave input is given by: snr = (6.02n + 1.76db) where n is the number of bits. thus the snr is a function of the resolution of the a/d. for an ideal 12-bit a/d the snr is equal to 74db. a fast fourier transform(fft) plot of the figure 17a. f in = 1khz, f s = 25khz, snr = 72.92db figure 19. f in 1 = 2.6khz, f in 2 = 3.1khz, f s = 25khz figure 17b. f in = 12khz, f s = 25khz, snr = 72.23db figure 18. ltc1289 enob vs input frequency frequency (khz) 0 6 effective number of bits 7 8 9 10 11 12 10 20 30 40 ltc1289 ?aif18 50 f s = 25khz snr ?1.76db 6.02 n = frequency (khz) 0 ?0 ?0 0 610 lt c1289 f17a ?0 ?00 24 81214 ?20 ?40 ?0 magnitude (db) frequency (khz) 0 ?0 ?0 0 610 lt c1289 f17b ?0 ?00 24 81214 ?20 ?40 ?0 magnitude (db) frequency (khz) 0 ?0 ?0 0 610 lt c1289 f19 ?0 ?00 24 81214 ?20 ?40 ?0 magnitude (db)
22 ltc1289 1289fb u s a o pp l ic at i wu u i for atio figure 19 shows an fft plot of the output spectrum for two tones applied to the input of the a/d. nonlinearities in the a/d will cause distortion products at the sum and differ- ence frequencies of the fundamentals and products of the fundamentals. this is classically referred to as intermodulation distortion (imd). 8. overvoltage protection applying signals to the analog mux that exceed the positive or negative supply of the device will degrade the accuracy of the a/d and possibly damage the device. for example this condition would occur if a signal is applied to the analog mux before power is applied to the ltc1289. another example is the input source is operating from different supplies of larger value than the ltc1289. these conditions should be prevented either with proper supply sequencing or by use of external circuitry to clamp or current limit the input source. as shown in figure 20, a 1k ? resistor is enough to stand off 15v (15ma for one only channel). if more than one channel exceeds the supplies than the following guidelines can be used. limit the current to 7ma per channel and 28ma for all channels. this means four channels can handle 7ma of input current each. reducing the aclk and sclk frequencies from the maximum of 2mhz and 1mhz, respectively (see typical peformance characteristics curves maximum aclk fre- quency vs source resistance and sample and hold acqui- sition time vs source resistance) allows the use of larger current limiting resistors. use 1n4148 diode clamps from the mux inputs to v cc and v if the value of the series resistor will not allow the maximum clock speeds to be used or if an unknown source is used to drive the ltc1289 mux inputs. how the various power supplies to the ltc1289 are applied can also lead to overvoltage conditions. for single supply operation (i.e., unipolar mode), if v cc and ref + are not tied together, then v cc should be turned on first, then ref + . if this sequence cannot be met, connecting a diode from ref + to v cc is recommended (see figure 21). for dual supplies (bipolar mode) placing two schottky diodes from v cc and v to ground (figure 22) will prevent power supply reversal from occuring when an input source is applied to the analog mux before power is applied to the device. power supply reversal occurs, for example, if the input is pulled below v then v cc will pull a diode drop below ground which could cause the device not to power up properly. likewise, if the input is pulled above v cc then v will be pulled a diode drop above ground. if no inputs are present on the mux, the schottky diodes are not required if v is applied first, then v cc . because a unique input protection structure is used on the digital input pins, the signal levels on these pins can exceed the device v cc without damaging the device. 3.3v ltc1289 aif20 dgnd v agnd v cc 1k ltc1289 ch0 v in 3.3v 0.1 f 22 f figure 20. overvoltage protection for mux 3.3v ltc1289 aif21 ref + v cc ltc1289 22 f 1n4148 v ref 14 20 figure 21. 3.3v ltc1289 aif22 dgnd v agnd v cc ltc1289 3.3v 0.1 f 22 f 1n5817 1n5817 figure 22. power supply reversal
23 ltc1289 1289fb a ?uick look?circuit for the ltc1289 users can get a quick look at the function and timing of the ltc1289 by using the following simple circuit. ref + and d in are tied to v cc selecting a 3v input span, ch7 as a single-ended input, unipolar mode, msb-first format and 16-bit word length. aclk is driven by an external clock and sclk is driven by one half the clock rate. cs is driven at 1/128 the clock rate by the 74hc393 and d out outputs the data. all other pins are tied to a ground plane. the output data from the d out pin can be viewed on an oscilloscope which is set up to trigger on the falling edge of cs. a ?uick look?circuit for the ltc1289 scope trace of ltc1289 ?uick look?circuit showing a/d output of 010101010101 (555 hex ) u s a o pp l ic at i ty p i ca l ltc1289 ta02 ltc1289 0.1 f 22 f f cho ch1 ch2 ch3 ch4 ch5 ch6 ch7 com dgnd v in { to oscilloscope 74hc393 a1 clr1 1qa 1qb 1qc 1qd gnd v cc a2 clr2 2qa 2qb 2qc 2qd clock in 2mhz max 3.0v f/2 f/128 v cc aclk sclk d in d out cs ref + ref v agnd aclk sclk cs d out msb (b11) deglitcher time lsb (b0) fills zeroes vertical: 5v/div horizontal: 2 s/div sneak-a-bit tm the ltc1289? unique ability to software select the polar- ity of the differential inputs and the output word length is used to achieve one more bit of resolution. using the circuit below with two conversions and some software, a 2? complement 12-bit + sign word is returned to memory inside the mpu. the mc68hc05c4 was chosen as an example, however, any processor that operates at 3.3v could be used. two 12-bit unipolar conversions are performed: the first over a 0v to 2.5v span and the second over a 0v to 2.5v span (by reversing the polarity of the inputs). the sign of the input is determined by which of the two spans con- tained it. then the resulting number (ranging from 4095 to +4095 decimal) is converted to 2? complement nota- tion and stored in ram. 2.5v 1st conversion (+) ch6 (? ch7 0v 0v 1st conversion 4096 steps 2nd conversion 4096 steps 2.5v 2nd conversion (? ch6 (+) ch7 0v v in v in 2.5v 2.5v software 8191 steps ltc1289 ta04 sneak-a-bit sneak-a-bit is a trademark of linear technology corp. sneak-a-bit circuit ltc1289 ta03 10 f 22 f lt1019 ?.5 mc68hc05c4 sclk mosi miso co 1k ?.3v 0.1 f 2mhz aclk +3.3v other channels or sneak-a-bit inputs v in ?.5v to +2.5v ltc1289 cho ch1 ch2 ch3 ch4 ch5 ch6 ch7 com dgnd v cc aclk sclk d in d out cs ref + ref v agnd
24 ltc1289 1289fb lda #$50 configuration data for spcr sta $0a load configuration data into $0a lda #$ff configuration data for port c ddr sta $06 load configuration data into port c ddr bset 0, $02 make sure cs is high jsr read ?+ dummy read configures ltc1289 for next read jsr read +/ read ch6 with respect to ch7 jsr read ?+ read ch7 with respect to ch6 jsr chk sign determines which reading has valid data, converts to 2's complement and stores in ram read / + : lda #$3f load d in word for ltc1289 into acc jsr transfer read ltc1289 routine lda $60 load msbs from ltc1289 in acc sta $71 store msbs in $71 lda $61 load lsbs from ltc1289 in acc sta $72 store lsbs in $72 rts return u s a o pp l ic at i ty p i ca l sneak-a-bit code for the ltc1289 using the mc68hc05c4 sneak-a-bit code sneak-a-bit code for the ltc1289 using the mc68hc05c4 mnemonic description d out from ltc1289 in mc68hc05c4 ram location $77 b12 b11 b10 b9 b8 b7 b6 b5 location $87 b4 b3 b2 b1 b0 filled with 0s d in words for ltc1289 sign lsb mux addr. uni msbf word length d in 1 0 0 1 1 1 1 1 1 d in 2 0 1 1 1 1 1 1 1 d in 3 0 0 1 1 1 1 1 1 (odd/sign) ltc1289 ta05 mnemonic description read +/? lda #$7f load d in word for ltc1289 into acc jsr transfer read ltc1289 routine lda $60 load msbs from ltc1289 into acc sta $73 store msbs in $73 lda $61 load lsbs from ltc1289 into acc sta $74 store lsbs in $74 rts return transfer: bclr 0, $02 cs goes low sta $0c load d in into spi. start transfer loop 1: tst $0b test status of spif bpl loop 1 loop to previous instruction if not done lda $0c load contents of spi data reg into acc sta $0c start next cycle sta $60 store msbs in $60 loop 2: tst $0b test status of spif bpl loop 2 loop to previous instruction if not done bset 0, $02 cs goes high lda $0c load contents of spi data reg into acc sta $61 store lsbs in $61 rts return chk sign: lda $73 load msbs of +/?read into acc ora $74 or acc (msbs) with lsbs of +/?read beq minus if result is 0 goto minus clc clear carry ror $73 rotate right $73 through carry ror $74 rotate right $74 through carry lda $73 load msbs of +/?read into acc sta $77 store msbs in ram locations $77 lda $74 load lsbs of +/?read into acc sta $87 store lsbs in ram location $87 bra end goto end of routine minus: clc clear carry ror $71 shift msbs of ?+ read right ror $72 shift lsbs of ?+ read right com $71 1's complement of msbs com $72 1's complement of lsbs lda $72 load lsbs into acc add #$01 add 1 to lsbs sta $72 store acc in $72 clra clear acc adc $71 add with carry to msbs. result in acc sta $71 store acc in $71 sta $77 store msbs in ram locations $77 lda $72 load lsbs in acc sta $87 store lsbs in ram location $87 end: rts return
25 ltc1289 1289fb u s a o pp l ic at i ty p i ca l power shutdown for battery-powered applications it is desirable to keep power dissipation at a minimum. the ltc1289 can be powered down when not in use reducing the supply current from a nominal value of 1ma to typically 1 a (with aclk turned off). see the curve for supply current (power shutdown) vs aclk if aclk cannot be turned off when the ltc1289 is powered down. in this case the supply current is proportional to the aclk frequency and is independent of temperature until it reaches the magnitude of the supply current attained with aclk turned off. as an example of how to use this feature let? add this to the previous application, sneak-a-bit. after the chk sign subroutine call insert the following: jsr chk sign determines which reading has valid data, converts to 2? complement and stores in ram jsr shutdown ltc1289 power shutdown routine the actual subroutine is: shutdown: lda #$3d load d in word for ltc1289 into acc jsr transfer read ltc1289 routine rts return to place the device in power shutdown the word length bits are set to wl1 = 0 and wl0 = 1. the ltc1289 is powered up on the next request for conversion and it's ready to digitize an input signal immediately. power shutdown timing considerations after power shutdown has been requested, the ltc1289 is powered up on the next request for a conversion. this request can be initiated either by bringing cs low or by starting the next cycle of sclks if cs is kept low (see figures 3 and 4). when the sclk frequency is much slower than the aclk frequency a situation can arise where the ltc1289 could power down and then prema- turely power back up. power shutdown begins at the negative going edge of the 10th sclk once it has been requested. a dummy conversion is executed and the ltc1289 waits for the next request for conversion. if the sclks have not finished once the ltc1289 has finished its dummy conversion, it will recognize the next remaining sclks as a request to start a conversion and power up the ltc1289 (see figure 23). to prevent this, bring either cs high at the 19th sclk (figure 24) or clock out only 10 sclks (figure 25) when power shutdown is requested. figure 23. power shutdown timing problem figure 24. power shutdown timing 110 sclk cs power shutdown starts dummy conversion finishes after 52 aclk periods power up ltc1289 taf23 110 sclk cs power shutdown starts dummy conversion finishes after 52 aclk periods power up ltc1289 taf24
26 ltc1289 1289fb u s a o pp l ic at i ty p i ca l package descriptio u 110 sclk cs power shutdown starts dummy conversion finishes after 52 aclk periods power up ltc1289 taf2 figure 25. power shutdown timing j package 20-lead cerdip (narrow .300 inch, hermetic) (reference ltc dwg # 05-08-1110) j20 1298 3 7 56 10 9 1 4 2 8 11 20 16 15 17 14 13 12 19 18 0.005 (0.127) min 0.025 (0.635) rad typ 0.220 ?0.310 (5.588 ?7.874) 1.060 (26.924) max 0 ?15 0.008 ?0.018 (0.203 ?0.457) 0.015 ?0.060 (0.381 ?1.524) 0.125 (3.175) min 0.014 ?0.026 (0.356 ?0.660) 0.045 ?0.065 (1.143 ?1.651) 0.100 (2.54) bsc 0.200 (5.080) max 0.300 bsc (0.762 bsc) 0.045 ?0.068 (1.143 ?1.727) full lead option 0.023 ?0.045 (0.584 ?1.143) half lead option corner leads option (4 plcs) note: lead dimensions apply to solder dip/plate or tin plate leads obsolete package
27 ltc1289 1289fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representation that the interconnection of circuits as described herein will not infringe on existing patent rights. package descriptio u n20 0405 .020 (0.508) min .120 (3.048) min .125 ?.145 (3.175 ?3.683) .065 (1.651) typ .045 ?.065 (1.143 ?1.651) .018 .003 (0.457 0.076) .005 (0.127) min .255 .015* (6.477 0.381) 1.060* (26.924) max 12 3 4 5 6 7 8 910 19 11 12 13 14 16 15 17 18 20 .008 ?.015 (0.203 ?0.381) .300 ?.325 (7.620 ?8.255) .325 +.035 ?015 +0.889 0.381 8.255 () note: 1. dimensions are inches millimeters *these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 inch (0.254mm) .100 (2.54) bsc n package 20-lead pdip (narrow .300 inch) (reference ltc dwg # 05-08-1510)
28 ltc1289 1289fb package descriptio u linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 1992 lt 0506 rev b ?printed in usa related parts part number description comments ltc1285/ltc1288 1-/2-channel, 3v, micropower 12-bit adc autoshutdown, so-8 package ltc1290 8-channel configurable, 5v, 12-bit adc pin-compatible with ltc1289 ltc1391 serial-controlled 8-to-1 analog multiplexer low r on , low power, 16-pin so and ssop package ltc1401 3v, 12-bit, 200ksps serial adc 15mw, internal reference, so-8 package ltc1448 dual 12-bit v out dacs in so-8 package 0.5lbs dnl, 3v to 5v supply, swings 0v to v ref ltc1454/ltc1454l dual 12-bit v out dacs in so-16 package 5v/3v, buffered rail-to-rail output, 0.5lsb dnl ltc1458/ltc1458l quad 12-bit v out dacs 5v/3v, buffered rail-to-rail output, 0.5lsb dnl ltc1594/ltc1598l 4-/8-channel, 3v micropower 12-bit adc low power, small size ltc1852/ltc1853 10-bit/12-bit, 8-channel, 400ksps adcs 3v or 5v, programmable mux and sequencer ltc2404/ltc2408 24-bit, 4-/8-channel, no latency ? adc 4ppm inl, 10ppm total unadjusted error, 200 a ltc2424/ltc2428 20-bit, 4-/8-channel, no latency ? adc 1.2ppm noise, 8ppm inl, pin compatible with ltc2404/ltc2408 s20 (wide) 0502 note 3 .496 ?.512 (12.598 ?13.005) note 4 20 n 19 18 17 16 15 14 13 1 23 4 5 6 78 .394 ?.419 (10.007 ?10.643) 910 n/2 11 12 .037 ?.045 (0.940 ?1.143) .004 ?.012 (0.102 ?0.305) .093 ?.104 (2.362 ?2.642) .050 (1.270) bsc .014 ?.019 (0.356 ?0.482) typ 0 ?8 typ note 3 .009 ?.013 (0.229 ?0.330) .016 ?.050 (0.406 ?1.270) .291 ?.299 (7.391 ?7.595) note 4 45 .010 ?.029 (0.254 ?0.737) .420 min .325 .005 recommended solder pad layout .045 .005 n 1 2 3 n/2 .050 bsc .030 .005 typ .005 (0.127) rad min inches (millimeters) note: 1. dimensions in 2. drawing not to scale 3. pin 1 ident, notch on top and cavities on the bottom of packages are the manufacturing options. the part may be supplied with or without any of the options 4. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .006" (0.15mm) sw package 20-lead plastic small outline (wide .300 inch) (reference ltc dwg # 05-08-1620)

▲Up To Search▲

Price & Availability of LTC1289CCSWTRPBF

	To Download LTC1289CCSWTRPBF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .